RLC (Oct 10 2026 at 11:35): RLC (Oct 10 2026 at 11:35):Hello. In the future gone be or there's any plan to increase the capabilities of the compiler for AVX, AVX2 and AVX512 instructions or it's better to maintain in a platform specific way. Because for parsing and specific checksum and other algorithm are benefit of that. Thank you for the help.
notramo (Oct 10 2026 at 11:42):https://www.roc-lang.org/docs/main/Num/#U8x16
notramo (Oct 10 2026 at 11:42):@RLC, are you looking for something like this?
RLC (Oct 10 2026 at 11:43):notramo said in #beginners > Doubt about SIMD availability:
that's 128 bit register it's from the SSE instruction set. AVX, AVX2 have 256 bit if implemented should look something like U8x32 and U8x64 in the AVX512 standard
RLC (Oct 10 2026 at 11:45):I kinda need registers as big as my CPU can handle. The why im asking it's cause im making a simd csv parser (for the love of the game) and kinda need that big registers for handling as many data as possible in every iteration.
notramo (Oct 10 2026 at 11:48):I don't know whether it will be available in future versions.
notramo (Oct 10 2026 at 11:49):I recommend writing your parsers with the U8x16 type, because the logic is the same.
notramo (Oct 10 2026 at 11:49):And if wider SIMD support is added later, you can simply do a find-and-replace in your code.
notramo (Oct 10 2026 at 11:51):The future is scalable vector length anyways. Dynamically select at runtime, instead of hardcoding into the codebase.
RLC (Oct 10 2026 at 11:52):notramo said:
I recommend writing your parsers with the U8x16 type, because the logic is the same.
that's what i'm doing already. The edge cases gone be the same even with wider registers. But isn't just for wider registers too there's some algebraic operations that can be useful in detection of edge cases using bitmasking. thank you
Anton (Oct 10 2026 at 11:53):RLC said:
cause im making a simd csv parser
I am not sure what Luke's code ends up like under the hood but he recently made a fast csv parser:
notramo (Oct 10 2026 at 11:54):I wonder how Roc is going to handle RISC-V and ARM dynamic vector size.
RLC (Oct 10 2026 at 11:59):Anton said:
RLC said:
cause im making a simd csv parser
I am not sure what Luke's code ends up like under the hood but he recently made a fast csv parser:
Yeah it's using simd behind for the UTF-8 parsing i read pretty fast now i have to study with more time his codebase. thank you.
Last updated: Oct 15 2026 at 17:56 UTC